1. Field of the Invention
The present invention is related to semiconductor devices and manufacturing and more particularly to high performance field effect transistors (FETs) and methods of manufacturing high performance FETs.
2. Background Description
Typical semiconductor integrated circuit (IC) design goals include high performance and density at minimum power. To minimize semiconductor circuit power consumption, most ICs are made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. A typical CMOS circuit drives a purely or nearly pure capacitive load and includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Performance depends upon how fast the CMOS circuit can charge and discharge the capacitive load, i.e., the circuit's switching speed. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as a simple open switch) and, vice versa. The switch is open, i.e., the device is off, when the magnitude of the gate to source voltage (Vgs) is less than some threshold voltage (VT) with respect to its source. So, ideally, an NFET is off when its Vgs is below VT, and on, conducting current above VT. Similarly, a PFET is off when its gate voltage, Vgs, is above its VT, i.e., less negative, and on below VT.
A CMOS inverter, for example, is a PFET and NFET pair that are series connected between a power supply voltage (Vdd) and ground (GND), both gated by the same input signal. Circuit performance is a measure of how fast both drive the same capacitive load. At one input signal state the PFET is active or on pulling the output high, with device source to drain current (Isd) or on current (Ionp) charging the load capacitance to Vdd. At the opposite input signal state the NFET is active or on pulling the output low with device drain to source (Ids) or on current (Ionn) discharging the load capacitance back to ground. Typically, circuit designers select devices such that the rise and fall times are equal and so, by design, Ion=Ionp=−Ionn. Device on current is related to gate, source and drain voltages and, depending upon those voltages, the device may be modeled as a voltage controlled current source or a resistor. Other types of elemental CMOS-type circuits (namely, transmission gate circuits with parallel connection of NFET and PFET and various dynamic logic circuits) have also been widely employed in modem digital circuits. Despite different styles of CMOS circuits, the basic design and operation principles can be traced using a simple inverter circuit.
Semiconductor technologies and chip manufacturing are continually advancing towards higher circuit switching frequency (circuit performance) and an increased number of transistors per given area (circuit density). To pack more function in the same area, chip feature sizes and, correspondingly, supply voltage are steadily decreasing. Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency. So, unfortunately, not withstanding the decrease of chip supply voltage and capacitive load, chip active power consumption has slowly increased. In addition, as FET features have shrunk, what are collectively known as short channel effects have become pronounced resulting in a rapid increase of stand-by power consumption. Short channel effects mainly include a transistor VT reduction as the gate length is reduced. Such VT dependence on the gate length is also known as VT roll-off. Accordingly, a slight variation of transistor gate length leads to a relatively large variation of the transistor threshold voltage VT and, consequently, to a substantially increased leakage for transistors with shorter gates. Furthermore, in order to keep a gradual VT roll-off, the transistor gate insulator is generally made thinner. This, in turn, results in increased gate leakages or gate induced leakages (i.e., gate to channel, gate to source or drain and gate induced drain leakage (GIDL)). Therefore, for circuits with transistor gate length of smaller than about 100 nm, the stand-by power dissipation has become comparable to the active power dissipation. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power.
High-performance FET structures are designed to reduce VT dependence on gate length while providing the highest drive current at a specified overall off or leakage current. One approach to reducing short channel effects include shallow source/drain extensions. Essentially, after patterning gates on a wafer, a shallow and high dose dopant extension implant is performed. The extension implant forms source/drain extensions and is performed independently for each type of device with the aid of block masks. Extensions may also be performed after forming a thin offset spacer for certain types of devices. After performing an extension implant, thick spacers are formed at each end of FET gates. The spacer blocks or attenuates the higher energy deep source/drain dopant implant at the areas adjacent to the gates, spacing the source/drain diffusion regions away from the gate. An activation anneal is then conducted to activate both extension and source/drain dopants. During the activation anneal the implanted extension dopants diffuse and form an overlap with gate. While, the excessive diffusion of dopants during the activation anneal is not desirable, the presence of an overlap between the gate and the source/drain extension is a requirement for a proper device operation. The extension/gate overlap can be also achieved via an angled extension implant. Accordingly, a shallow source/drain extension is formed between the deep source/drain regions and the gate. After the activation anneal, the source/drain regions are silicided to minimize series resistance within source/drain regions.
The parasitic series resistance of source/drain silicide is often so small that its contribution to the total series resistance of a typical MOSFET is considered to be negligible and not a limiting factor to the device performance. The series resistances of a typical MOSFET device which affect its performance are (1) the source/drain silicide contact resistance (between the silicide and doped silicon), (2) the resistance of the doped source/drain regions under the silicide, (3) the extension resistance, and (4) the spreading resistance between the extension and the channel. In order to minimize the extension resistance, the extensions should be made very short. A typical extension is formed as a shallow dopant region having electrical conductivity substantially lower than that of a typical silicide. A typical extension depth in a modem MOSFET devices is less than about 50 nm and could be as shallow as 10 nm. A typical total spacer thickness that separates the gate edge and the silicided region is from about 300 Å in advanced NFET devices to about 600 Å in typical NFET and PFET devices. Due to the combined effects of relatively low electrical conductivity and relatively shallow depth, an extension may introduce a substantial series resistance, thereby impeding current flow through the transistor. For this reason, the extension is made as short as possible.
A typical silicidation process begins with depositing metal such as Ni, Co, or Ti onto a clean source/drain surface, followed by heating the wafer to react metal and silicon. The unreacted metal can be easily removed by a solution of strong acid (e.g. sulfuric acid) selective to the silicide. The problem with this technique is that the silicide forms under the spacer due to the generally isotropic nature of the diffusion processes involved in intermixing silicon and metal atoms. In addition, the silicide/silicon interfaces are usually very non-uniform due to “spiking” of the silicide into the silicon beyond the boundary defined by an ideal isotropic diffusion process. The lateral “roughness” of the silicide can be considerable due to various factors which enhance silicide growth under the spacer. Examples of such enhanced silicide growth include a preferred growth of the silicide along certain crystal orientations, preferred growth of the silicide in locally stressed areas, and/or preferred growth of the silicide in areas with high concentration of silicon crystal defects. These factors present a high probability that the silicide will breach through highly-doped source/drain and extension region and come into a direct contact with the channel or transistor body, effectively degrading transistor performance and increasing leakage and power consumption. If the silicide comes into direct contact with the transistor channel, the effective contact resistance between the silicide and the channel will become very high due to a relatively low channel carrier concentration in the channel and the resultant wide Schottky barrier. Further, if the silicide comes into direct contact with the transistor body, the barrier height of resultant Schottky diode is substantially lower than that of a typical p-n junction resulting in an increased leakage and increased circuit power consumption.
If the thickness of the spacer that separates the silicided region from the gate is increased sufficiently that the probability of the silicide coming into direct contact with the transistor channel and body is low, then the series resistance of the extension is increased. High extension resistance reduces device currents and increases the resistance charging the load capacitance which degrades circuit performance. Consequently, sensitivity to external series device resistance is exacerbated.
An extremely thin (˜10 Å–100 Å) highly doped region between the silicide and the channel is highly desirable. Such a thin highly doped region would reduce the silicide contact resistance to normal levels and would make the extension resistance negligible. Unfortunately, such ultra thin doped layer between the region silicide and the transistor channel has been unattainable due to the silicide breaching through the doped layer.
Thus there is a need to reduce the source/drain extension resistance and, more particularly, to minimize silicide/silicon interface roughness and prevent silicide-based electrical shorts.